Field
Implementations described herein generally relate to the processing of substrates, and more particularly relate to methods for forming tungsten materials on substrates using vapor deposition processes.
Description of the Related Art
Reliably producing nanometer-sized features is one of the key technologies for the next generation of semiconductor devices. The shrinking dimensions of circuits and devices have placed additional demands on processing capabilities. The multilevel interconnects that lie at the heart of integrated circuit technology require precise processing of high aspect ratio features, such as vies and other interconnects. Reliable formation of these interconnects is very important to future success and to the continued effort to increase circuit density and quality of individual substrates.
Metallization of features formed on substrates includes CVD deposition of metals such as tungsten. Tungsten can be used for metal fill of source contacts, drain contacts, metal gate fill and gate contacts as well as applications in DRAM and flash memory. With technology node shrinkage, tungsten films having low resistivity and low roughness are desirable for device characteristics and for integration with subsequent processes.
Chemical vapor deposition (CVD) is one process technology used for metal fill of tungsten. A pattern is etched in the underlying interlayer dielectric (ILD) material 10. Tungsten is then processed to fill the etched substrates.
But successive reduction in feature sizes has meant that there is increasing difficulty in this process. When the tungsten layer is formed on the sidewalls as well as the bottom surface of the feature, the CVD process deposits the metal on both surfaces within the feature. With high aspect ratio features, as can be seen in Hal which shows the result of tungsten deposition growth during CVD, the opening (in new generation devices—where the nominal feature gap opening dimensions are in the range of 32 nm and less—(gap in the surface of the dielectric material layer created by the feature (or depression) therein can be 32 nm or less)) of the feature can become “closed off” 27 before the bottom up fill process reaches the full height of the thickness of the dielectric layer to fully fill the feature with substantially void-free tungsten fill material. The tungsten growth on the sidewalls tends to close off the feature at the feature opening before the lower portion of the feature has completely grown from the feature bottom surface resulting in a void 30 forming within the feature. The presence of the void 30 changes the material and operating characteristics of the interconnect feature and may eventually cause improper operation and premature breakdown of the device. The conductive element, line, to be efficient, carries near its practical maximum current density as established and known by persons skilled in the art in current state of the art devices. The goal is to achieve the same current flow density or higher in smaller features in future devices.
Therefore, it is desirable to use CVD for void-free filling of high aspect ratio ultra-small features with tungsten without the problems and limitations of conventional techniques discussed above.